Characterization of pGaN-gate power HEMTs

Abstract

This thesis presents a comprehensive study of p-GaN gate GaN High Electron Mobility Transistors (HEMTs) with a focus on understanding how fabrication process variations and gate structural designs impact key electrical performance metrics. Five industry-fabricated wafers, each processed with distinct etch depths, contact strategies, and p-GaN surface configurations, were characterized using a combination of DC and pulsed I–V measurements. Full-transistor modules were evaluated alongside specialized test structures to enable both system-level and localized analysis. DC measurements using the Keysight B1505A system revealed that more aggressive gate contact schemes improved ON-resistance and transconductance, but often at the cost of increased gate leakage and reduced threshold control. Pulsed-IV characterization with the Auriga AU4750 system uncovered dynamic Ron degradation behavior and charge trapping effects, especially under high drain bias conditions. Extracted time constants demonstrated process-dependent trends, with wafers retaining more of the p-GaN surface exhibiting slower charge detrapping and more severe transient effects. Specialized test structures provided additional insights into gate lateral conduction, sheet resistance, and contact asymmetry, reinforcing the connection between device layout, processing, and observed variability. These findings highlight critical trade-offs in the design and fabrication of p-GaN gate GaN HEMTs and offer design-aware strategies for optimizing performance and reliability.